1. Field of the Invention
The present invention relates to a field of semiconductor integrated circuit (IC) manufacturing, and more specifically, to a dielectric separator layer to reduce electromigration and a method of making such a dielectric separator layer.
2. Discussion of Related Art
In 1965 Gordon Moore observed that the pace of technology innovation resulted in a doubling of a number of devices per unit area on an IC chip about every 18 months. Over the ensuing decades, the semiconductor industry has adhered closely to a schedule projected by Moore's Law for improving device density.
Maintaining such an aggressive schedule for each device generation has required continual enhancements at the corresponding technology node. Devices on a chip are fabricated from a semiconductor, such as silicon, that is isolated with an electrical insulator, such as silicon oxide. The devices are connected with an electrical conductor, such as copper, stacked in layers that are separated vertically and horizontally by the electrical insulator.
Additive processes, such as oxidation, deposition, and ion implantation have been improved to produce the requisite doping profiles and film stacks across the chip. Subtractive processes, such as wet etch, dry etch, and chemical-mechanical polish have also been improved to maintain pattern fidelity of the features across the chip.
Photolithography was enhanced to keep up with a reduction in the critical dimension (CD) needed for each device generation. However, improving the resolution that could be achieved often required compromising the depth of focus (DOF). As a result, the smaller DOF made it necessary to minimize the topography across the substrate in which the device was being formed. Thus, planarization of the surface of the substrate with chemical-mechanical polish (CMP) became necessary to fabricate advanced devices.
In order to improve device density, both the transistor in the front-end of semiconductor processing and the interconnect in the back-end of semiconductor processing have to be scaled down. The scaling of the transistor and the scaling of the interconnect must be carefully balanced to avoid degrading performance or reliability of the chip.
The switching speed of the transistor may be adversely impacted by an excessively large resistance-capacitance (RC) product delay in the interconnect. Resistance in the interconnect may be reduced by using an electrically conducting material with a low resistivity. Capacitance in the wiring may be reduced by using an electrically insulating material with a low dielectric constant (k).
However, the electrically insulating material with a low dielectric constant must also have high mechanical strength to withstand the rigors of front-end and back-end of semiconductor processing, as well as, the packaging steps.
Thus, what is needed is an electrically insulating material with low dielectric constant and high mechanical strength and a method of making such an electrically insulating material.